1. Field of the Invention
The present invention relates to a display device in which a light emitting element is provided on an insulting surface, the present invention particularly relates to an active matrix display device having a plurality of pixels arranged in matrix, and in each pixel a light emitting element is arranged. Further, the present invention relates to electronic apparatuses applying the display device.
2. Description of the Related Art
An active matrix display device having a plurality of pixels in which a switching element and a light emitting element are arranged in each pixel, comes under the spotlight.
For the light emitting element arranged in each pixel, an OLED (organic light emitting diode) device has OLEDs included in is described as an example.
In this specification, an OLED denotes a configuration having an anode, a cathode, and an organic component layer sandwiched between the anode and the cathode. The anode and the cathode correspond to a first and a second electrode, respectively. Then, an OLED emits light by applying a voltage between electrodes.
An organic compound layer usually has a laminate structure. A typical laminate structure thereof is one proposed by Tang et al. of Eastman Kodak Company and consisting of a hole transporting layer, a light emitting layer, and an electron transporting layer. Other examples of the laminate structure include one in which a hole injection layer, a hole transporting layer, a light emitting layer, and an electron transporting layer are layered in order on an anode, and one in which a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injection layer are layered in order on an anode. A light emitting layer may be doped with a fluorescent pigment or the like.
In this specification, all layers provided between the anode and the cathode generally are called an organic compound layer. The above-mentioned hole injection layer, hole transporting layer, light emitting layer, electron transporting layer, electron injection layer, and other layers are all included in the organic compound layer.
A given voltage is applied to an organic compound layer structured as above from a pair of electrodes (an anode and a cathode) to induce recombination of carriers in its light emitting layer. As a result, the light emitting layer emits light. Note that in this specification, emitting an OLED is referred to as driving an OLED.
An OLED in this specification refers to an OLED that uses a singlet exciton to emit light (fluorescent light), an element that uses a triplet exciton to emit light (phosphorescent light), or an OLED that uses the both.
Further, any one of a low molecular material, a high molecular material, and an intermediate molecular material can be a material for an organic compound layer of OLED.
Note that an intermediate molecular material in this specification denotes a material without sublimeness and the length of a chain of its molecular is 10 μm or less.
An OLED display device has advantages like superiority in response, capable of operation with a low voltage and a wide view angle, etc. Therefore, the OLED display device comes under the spotlight as a next generation flat panel display.
FIG. 7 shows a schematic structure of an active matrix OLED display device.
Assume that a video signal inputted to a display device in this specification is a digital signal (hereinafter referred to as digital video signal).
In FIG. 7, a display device includes a pixel portion 704 having a plurality of pixels arranged in matrix, a signal line driver circuit 701, a scanning line driver circuit 703, and a signal control circuit 702.
Note that the signal control circuit 702 may be integrally formed on a substrate in which the pixel portion 704 is formed, or may be formed on a single crystalline IC substrate and mounted on the substrate in which the pixel portion 704 is formed.
A digital video signal (video signal) inputted from the outside of the display device is temporarily stored in the signal control circuit 702. After that, the digital video signal is read out from the signal control circuit 702 and inputted to the signal line driver circuit 701.
The signal line driver circuit 701 takes the digital video signal and outputs a video signal to a plurality of signal lines provided to the pixel portion 704. In addition, the scanning line driver circuit 703 inputs signals to a plurality of scanning lines provided to the pixel portion 704.
A specific pixel row is selected by the signals inputted to the plurality of scanning lines. Here, assume that the selection of the pixel row indicates that a pixel row is in a state in which the video signals outputted to the respective signal lines can be inputted to the respective pixels.
Thus, light emission of light emitting elements in the respective pixels is controlled according to the video signals inputted to the respective pixels by the signal line driver circuit 701 and the scanning line driver circuit 703.
Note that the video signal may be an analog signal or a digital signal. Further, the video signal may be a voltage signal or a current signal.
When an analog video signal is inputted, the light emitting element in each pixel emits light at an intensity corresponding to the inputted analog video signal, thereby representing a gray scale.
On the other hand, in the pixel to which the digital video signal is inputted, a light emitting state or a non-light emitting state of the light emitting element is selected. At this time, in each pixel, a period for which the light emitting state is selected is controlled to represent a gray scale (time gray scale method). Alternatively, in each pixel, an area which becomes the light emitting state is controlled to represent a gray scale (area gray scale method).
Structural examples of the signal line driver circuit 701 and the signal control circuit 702 as shown in FIG. 7 will be described below.
FIG. 8 is a block diagram showing structures of the signal line driver circuit 701 and the signal control circuit 702 as shown in FIG. 7.
In FIG. 8, the signal line driver circuit 701 is constructed to output an analog signal as a video signal.
Note that an example in which digital video signals inputted to the signal line driver circuit 701 are signals of 6 bits is indicated. In addition, the digital video signals of 6 bits are inputted for every bit from the signal control circuit 702 through six wirings (VD1, VD2, VD3, VD4, VD5, and VD6). Here, a wiring to which the digital video signal of a p-th (where p is a natural number of 1 to 6) bit is inputted is indicated by VDp.
FIG. 6 shows a list order of the digital video signals inputted to the signal line driver circuit 701 through the wirings VD1 to VD6. Note that SD (i, j)_g indicates a g-th bit signal for a pixel at i-th row and j-th column in FIG. 6.
During a period TA (1, 1), signals SD (1, 1)_1 to SD (1, 1)_6 are simultaneously inputted to the respective wirings VD1 to VD6. Thus, 6-bit signals for the pixel at 1st row and 1st column are inputted to the wirings VD1 to VD6 during the period TA (1, 1). Such operation is conducted during all periods TA (1, 1) to TA (y, x) so that the 6-bit signals corresponding to all the pixels are inputted to the wirings VD1 to VD6.
Note that the display device has pixels of y-row and x-column.
Also, in FIG. 8, the signal control circuit 702 has a CPU 801, a frame memory A 803, a frame memory B 804, a memory controller 805 for controlling reading of the signal from and writing of the signal into the frame memory A 803 and the frame memory B 804, and a display controller 802 for outputting a control signal such as a clock signal inputted to the signal line driver circuit 701 and the scanning line driver circuit 703.
The frame memory A 803 and the frame memory B 804 each have a capacity capable of storing digital video signals corresponding to a frame.
The digital video signals inputted to the display device are temporarily stored in the frame memory A 803 in response to signals from the CPU 801 and the memory controller 805. The digital video signals stored in the frame memory A 803 are read therefrom for every bit in response to signals from the CPU 801 and the memory controller 805 and outputted to the wirings VD1 to VD6.
Note that, while the digital video signals stored in the frame memory A 803 are read, digital video signals corresponding to a next frame are stored in order in the frame memory B 804. Thus, the frame memory A 803 and the frame memory B 804 are alternately used. Accordingly, the storage and the read and write of the digital video signal can be efficiently conducted.
The digital video signals inputted to the signal line driver circuit 701 are held in a first latch circuit 502 in response to a sampling pulse from a shift register 501. When the digital video signals corresponding to one pixel row are held in the first latch circuit 502, a latch pulse is inputted to a second latch circuit 503. Thus, the second latch circuit 503 holds the digital video signals corresponding to one pixel row which are held in the first latch circuit 502 at a time.
The digital video signals held in the second latch circuit 503 are inputted to a D/A converting circuit 504. The digital video signals inputted to the D/A converting circuit 504 are converted into analog signals and outputted as video signals to respective signal lines S1 to Sx.
A circuit example of the signal line driver circuit 701 having the structure shown in FIG. 8 is shown in a circuit diagram of FIG. 5. In FIG. 5, the same portion as in FIG. 8 is indicated using the same reference symbols and the description thereof is omitted here.
In FIG. 5, a portion 502_1 of the first latch circuit 502, a portion 503_1 of the second latch circuit 503, and a portion 504_1 of the D/A converting circuit 504 which correspond to a first signal line S1 are shown for a typical example.
A clock pulse S_CLK and an inverted clock pulse S_CLKB obtained by inverting a polarity of the clock pulse are inputted to the shift register 501. When a start pulse S_SP is inputted to the shift register 501, it outputs a sampling pulse to wirings 511_1 to 511_x.
When the sampling pulse outputted from the shift register 501 is inputted to the wiring 511_1, respective blocks 502a_1 to 502a_6 included in the portion 502_1 of the first latch circuit hold the digital video signals inputted to the wirings VD1 to VD6.
The sampling pulse is inputted in order to the wirings 511_1 to 511_x and the first latch circuit 502 holds the digital video signals corresponding to one pixel row.
After that, a latch pulse LP and an inverted latch pulse LPB obtained by inverting a polarity of the latch pulse LP are inputted to the second latch circuit 503. Then, respective blocks 503a_1 to 503a_6 in the portion 503_1 of the second latch circuit hold the digital video signals which are held in the blocks 502a_1 to 502a_6 of the portion 502_1 of the first latch circuit at a time.
The digital video signals of 6 bits which are held in the portion 503_1 of the second latch circuit are inputted to the portion 504_1 of the D/A converting circuit through wirings S1d—1 to S1d—6, converted into analog signals, and outputted to the signal line S1.
Such operation is conducted by the second latch circuit 503 and the D/A converting circuit 504 which correspond to all the signal lines S1 to Sx. Thus, the video signals are outputted to all the signal lines S1 to Sx.
Note that, when the second latch circuit 503 holds the digital video signals corresponding to one pixel row, the first latch circuit 502 starts to hold digital video signals corresponding to a next pixel row.
Such operation is conducted for digital video signals corresponding to all pixel rows, and the digital video signals of 6 bits corresponding to all the pixels are outputted.
Thus, the output of the analog video signals corresponding to a frame to the signal lines S1 to Sx is completed.
Here, it is desirable that the display device is operated at low power consumption. Particularly, it is strongly desirable that a display device mounted in a portable information device has low power consumption.
Also, multi gray scale display is not always required for an image to be displayed on the display device. For example, display in which the number of gray scales is reduced is sufficient for an idle screen of a mobile telephone or the like.
Therefore, an attempt is being made to reduce the number of bits of the signals of the signals used for gray scale display, of the digital video signals inputted to the display device in accordance with a set by a user, thereby reducing the power consumption of the display device.
Hereinafter, an example of a driving method in the case where the number of bits used for gray scale display is reduced and the signal line driver circuit shown in FIG. 5 is operated will be described.
Note that an example in the case where gray scale is represented using the upper 2 bits of a digital video signal is indicated here.
The digital video signals are inputted to the signal line driver circuit through the wirings VD1 to VD6. However, a structure is employed in which the D/A conversion is conducted using only the upper 2-bit signals inputted to the wirings VD1 and VD2 by the D/A converting circuit 504 and analog signals are outputted.
The case of a structure in which the D/A converting circuit 504 has a plurality of gray scale power source lines each set to voltages corresponding to gray scales is considered as an example. When an intensity is represented using the digital video signals of the upper 2 bits, the supply of voltages to the gray scale power source lines corresponding to the lower 4-bit signals which are not used for gray scale representation is stopped.
Thus, the display in which the number of bits of the digital video signals used for gray scale display is reduced can be conducted.
Also, in the example of the above driving method, only the upper 2 bits of the digital video signals are read from the frame memory of the signal control circuit. According to such a driving method, the number of read operations of the frame memory in the signal control circuit can be reduced.
Thus, the display in which the number of bits of the digital video signals used for gray scale display is reduced can be conducted.
According to the display device having the signal line driver circuit 701 as shown in FIGS. 5, 7, and 8 in the conventional example, even when the number of gray scales is reduced and display is conducted, the shift register 501 included in the signal line driver circuit 701 operates at the same frequency.
Also, in the first latch circuit 502 and the second latch circuit 503 which are included in the signal line driver circuit 701, blocks corresponding to the lower bits which are not used for gray scale display also operate in response to the sampling pulse from the shift register and the latch pulse, as in the case of general gray scale representation of 6 bits.
Accordingly, there is a problem in that power consumption in the case where the number of gray scales is reduced and the gray scale display is conducted cannot be greatly reduced as compared with power consumption in the case where the 6-bit gray scale display is conducted.